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| 74VHC175 Quad D-Type Flip-Flop May 2007 74VHC175 Quad D-Type Flip-Flop Features High Speed: fMAX = 210MHz (Typ.) at VCC = 5V Low power dissipation: ICC = 4A (Max.) at TA = 25C High noise immunity: VNIH = VNIL = 28% VCC (Min.) Power down protection is provided on all inputs Low noise: VOLP = 0.8V (Max.) Pin and function compatible with 74HC175 tm General Description The VHC175 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flipflops, independent of the Clock or D inputs, when LOW. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Order Number 74VHC175M 74VHC175SJ 74VHC175MTC Package Number M16A M16D MTC16 Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering number. Connection Diagram Pin Description Pin Names D0-D3 CP MR Q0-Q3 Q0-Q 3 Description Data Inputs Clock Pulse Input Master Reset Input True Outputs Complement Outputs (c)1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 74VHC175 Quad D-Type Flip-Flop Logic Symbol Functional Description The VHC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW-toHIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The VHC175 is useful for general logic applications where a common Master Reset and Clock are acceptable. Truth Table IEEE/IEC Inputs @ tn, MR = H Dn L H H = HIGH Voltage Level L = LOW Voltage Level Outputs @ tn+1 Qn L H Qn H L tn = Bit Time before Clock Pulse tn+1 = Bit Time after Clock Pulse Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. (c)1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 2 74VHC175 Quad D-Type Flip-Flop Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VIN VOUT IIK IOK IOUT ICC TSTG TL Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current DC VCC / GND Current Storage Temperature Parameter Rating -0.5V to +7.0V -0.5V to +7.0V -0.5V to VCC + 0.5V -20mA 20mA 25mA 50mA -65C to +150C 260C Lead Temperature (Soldering, 10 seconds) Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VIN VOUT TOPR tr , tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time, VCC = 3.3V 0.3V VCC = 5.0V 0.5V Parameter Rating 2.0V to +5.5V 0V to +5.5V 0V to VCC -40C to +85C 0ns/V 100ns/V 0ns/V 20ns/V Note: 1. Unused inputs must be held HIGH or LOW. They may not float. (c)1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 3 74VHC175 Quad D-Type Flip-Flop DC Electrical Characteristics TA = 25C Symbol VIH VIL VOH TA = -40C to +85C Max. Min. 1.50 0.7 x VCC 0.50 0.3 x VCC 0.50 0.3 x VCC 1.9 2.9 4.4 2.48 3.80 V V Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0-5.5 2.0 3.0-5.5 2.0 3.0 4.5 3.0 4.5 Conditions Min. 1.50 0.7 x VCC Typ. Max. Units V VIN = VIH or VIL IOH = -50A 1.9 2.9 4.4 2.0 3.0 4.5 IOH = -4mA IOH = -8mA VIN = VIH or VIL IOL = 50A 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.1 4.0 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 0.1 0.1 0.1 0.44 0.44 1.0 40.0 V IOL = 4mA IOL = 8mA VIN = 5.5V or GND VIN = VCC or GND IIN ICC Input Leakage Current Quiescent Supply Current 0-5.5 5.5 A A Noise Characteristics TA = 25C Symbol VOLP (2) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 5.0 Typ. 0.4 -0.4 Limits 0.8 -0.8 3.5 1.5 Units V V V V Conditions CL = 50pF CL = 50pF CL = 50pF CL = 50pF VOLV(2) VIHD(2) VILD(2) Note: 2. Parameter guaranteed by design. (c)1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 4 74VHC175 Quad D-Type Flip-Flop AC Electrical Characteristics TA = 25C Symbol fMAX TA = -40C to +85C Min. 75 45 125 75 11.5 15.0 7.3 9.3 10.1 13.6 6.4 8.4 1.5 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 13.5 17.0 8.5 10.5 12.0 15.5 7.5 9.5 1.5 1.0 10 pF pF ns ns ns ns MHz Parameter Maximum Clock Frequency VCC (V) Conditions CL = 50pF Min. 90 50 150 85 Typ. 140 75 210 115 7.5 10.0 4.8 6.3 6.3 8.8 4.3 5.8 Max. Max. Units MHz 3.3 0.3 CL = 15pF 5.0 0.5 CL = 15pF CL = 50pF tPLH, tPHL Propagation Delay Time, (CP to Qn or Qn) 3.3 0.3 CL = 15pF CL = 50pF 5.0 0.5 CL = 15pF CL = 50pF tPLH, tPHL Propagation Delay Time, (MR to Qn or Qn) 3.3 0.3 CL = 15pF CL = 50pF 5.0 0.5 CL = 15pF CL = 50pF tOSLH, tOSHL Output to Output Skew CIN CPD Input Capacitance Power Dissipation Capacitance 3.3 0.3 CL = 50pF 5.0 0.5 CL = VCC (4) 50pF(3) = Open 4 44 10 Notes: 3. Parameter guaranteed by design. tOSLH = |tPLHmax - tPLHmin|; tOSHL =| tPHLmax - tPHLmin|. 4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD * VCC * fIN + ICC/4 (per F/F), and the total CPD when n pcs of the Flip-Flop operate can be calculated by the following equation: CPD (total) = 30 + 14 * n AC Operating Requirements TA = 25C Symbol Parameter VCC (V)(5) Typ. tW(L), tW(H) Minimum Pulse Width (CP) tW(L) tS tH tREC Minimum Pulse Width (MR) Minimum Setup Time (Dn to CP) Minimum Hold Time (Dn to CP) Minimum Removal Time (MR) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Note: 5. VCC is 3.3 0.3V or 5.0 0.5V 5.0 5.0 5.0 5.0 5.0 4.0 1.0 1.0 5.0 5.0 TA = -40C to +85C Units ns ns ns ns ns 5.0 5.0 5.0 5.0 5.0 4.0 1.0 1.0 5.0 5.0 Guaranteed Minimum (c)1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 5 74VHC175 Quad D-Type Flip-Flop Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A (c)1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 6 74VHC175 Quad D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D (c)1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 7 74VHC175 Quad D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. 5.000.10 4.55 5.90 4.45 7.35 0.65 4.40.1 1.45 5.00 0.11 12 MTC16rev4 Figure 3. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 (c)1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 8 74VHC175 Quad D-Type Flip-Flop TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Across the board. Around the world.TM ActiveArrayTM BottomlessTM Build it NowTM CoolFETTM CROSSVOLTTM CTLTM Current Transfer LogicTM DOMETM 2 E CMOSTM (R) EcoSPARK EnSignaTM FACT Quiet SeriesTM (R) FACT (R) FAST FASTrTM FPSTM (R) FRFET GlobalOptoisolatorTM GTOTM HiSeCTM (R) i-LoTM ImpliedDisconnectTM IntelliMAXTM ISOPLANARTM MICROCOUPLERTM MicroPakTM MICROWIRETM Motion-SPMTM MSXTM MSXProTM OCXTM OCXProTM (R) OPTOLOGIC (R) OPTOPLANAR PACMANTM PDP-SPMTM POPTM (R) Power220 (R) Power247 PowerEdgeTM PowerSaverTM Power-SPMTM (R) PowerTrench Programmable Active DroopTM (R) QFET QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM ScalarPumpTM SMART STARTTM (R) SPM STEALTHTM SuperFETTM SuperSOTTM -3 SuperSOTTM -6 SuperSOTTM -8 SyncFETTM TCMTM (R) The Power Franchise TM TinyBoostTM TinyBuckTM (R) TinyLogic TINYOPTOTM TinyPowerTM TinyWireTM TruTranslationTM SerDesTM (R) UHC UniFETTM VCXTM WireTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I26 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. No Identification Needed Full Production Obsolete Not In Production (c)1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 9 |
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